1) Project CR5 - A Real-Time Computer Network with Transparent Transport of Field Bus and LAN Data

Bearbeiter: Ahmad Obeid, Harald Richter

CR 5 is the fifth result of the long-term ‘CarRing‘ project, which has started in 2005. The first result of this project was CarRing I, which was a pure network simulation. The second result, CR II, was based on ten 32 bit soft-core processors of the Xilinx Microblaze type, which were synthesized for one Virtex 4 FPGA. These processors were run in parallel in order to execute protocols in software and cooperated with a bit serializer/deserializer in VHDL on the same FPGA that sent and received data with 1 Gbits/s as physical link speed. Then CR 3 followed, which was already a FPGA design in SystemC, that was realized completely in hardware without any CPU or software. It operated at a physical link speed of 3.125 Gb/s with a time resolution of 12.8 ns. The successor, CR 4, was a complete redesign of the SystemC code for the FPGA and implemented the first 3 ISO layers, as well as additional functions such as automatic periodic transmissions at prescribed points in time, multicast and global time. CR 4 could also improve the effective user bandwidth and reduce the end-to-end latency. CR4 was a significant step forward with respect to latency and functionality. The main feature of CR4 was its ‘Transparent Mode‘, which allows to connect in real time up to 4096 local area networks or field busses of all kinds and mixtures to the same amount of CR4 nodes. Each CR4 node transports its input data to any other node or node subset without user intervention. The user only has to configure which node serves for which field bus or local area network, and where the corresponding output nodes are located in a CR system. Application areas for CR 4 and its Transparent Mode are seen in real-time communication-systems inside of land, air, and space vehicles and in process and factory automation.
The successor, CR 5, is a complete redesign of the hardware of CR 4, including node and router boards. Now, price and miniaturization was an issue and again speed. The physical link speed we have now has increased from 3.125 Gb/s to 50 Gb/s at a cable length of 2,50 m which is considered to be the technical limit so far. Layers 1-3 of CR 5 were synthesized for a Kintex 7 FGPA, and 20 boards for CR 5 nodes and routers were developed and built and are now in the testing phase.
All CarRing subprojects were developed as a revival of ring-based topologies. It was shown that rings are useful for real-time data transfers in vehicles and machines for reasons of price, speed, cable lengths, weight and time-determinism. It was further shown that it is possible to implement highly-complex features of OSI layers solemnly in hardware by means of state-of-the-art SystemC synthesis tools without software or CPU. The project was funded by the German Science Foundation (DFG), as well as by companies such as Volkswagen or Lenze, for example.

2) Projekt TUCar - Eine Testplattform für Kommunikation und Steuergeräte im Auto

Bearbeiter: Maik Bartz

TUCar ist eine fahrende Testplattform zur Erprobung neuer Konzepte für Kommunikation und für Steuergeräte. TUCar soll für ein Auto der Zukunft die folgenden zwei Zielsetzungen erkunden und testen:

  • Eine verbesserte Datenübertragung zwischen allen Elektronikkomponenten
  • Eine Rezentralisierung der Steuergeräte (ECUs)

Für diese Punkte wurden die beiden Teilprojekte CarRing II bzw. ConPar definiert. Beim Teilprojekt CarRing II erfolgt die Intra-Auto-Kommunikation über ein EchtzeitRechnernetz anstelle von Feldbussen. Beim Teilprojekt ConPar wird eine Rezentralisierung der Steuergeräte durch Echtzeit-Emulation derselben in einem zuverlässigen Echtzeit-Parallelrechner durchgeführt. TUCar wurde zusammen mit dem Institut für Prozess- und Produktionsleittechnik der TU Clausthal entwickelt. Dieses Institut hat den mechanischen Teil des Projekts übernommen. TUCar wurde von der Volkswagen AG, der IAV GmbH und der Lenze GmbH gefördert.

3) Projekt Cloud-Efficient Modelling and Simulation of Magnetic Nano Materials

Bearbeiter: Pavel Ivanovic

The project applies cloud technology in material science and has an strong emphasis on algorithmic changes. It deals with the modelling and simulation of magnetic nano materials by means of a compute cloud, which is not yet efficiently possible. Magnetic materials can be described by the Maxwell equations and by the so-called Landau-Lifschitz-Gilbert equation (LLGE). The LLGE models the static and dynamic behaviour of small magnetic dipoles, which are created and manipulated in a material under the influence of an external magnetic write field. The goal of the project is the efficient numerical solution of the LLGE by means of a standard cloud as computing tool. The key feature of the proposal is that the algorithms and solvers needed for the LLGE are explicitly tailored to the specific properties compute clouds have, which are high intra-server and low inter-server communication performance. As a consequence, new algorithmic approaches must be devised, implemented and tested for solving the LLGE in a cloud in an efficient way. The goal is that all simulations needed for research on non-volatile nano-scale computer memories can be carried out in a standard compute cloud, because substantial algorithmic improvements in the solvers for the LLGE were made. The project will thus open-up the simulation and construction of future computer memories to a huge community of researchers, because sophisticated tools, such as scanning tunnel microscopes, supercomputers or parallel computers, are reduced.

Das Projekt wird vom Simulationswissenschaftlichen Zentrum Clausthal-Göttingen (SWZ) gefördert.

4) Projekt ConPar - Ein Parallelrechner zur Echtzeit-Emulation von Steuergeräten in Automobilen

Bearbeiter: Toni Kämmerer

ConPar ist ein Parallelrechner zur Emulation von Steuergeräten in Automobilen (ECUs). Seine Aufgabe ist es, kommerzielle ECUs in Echtzeit nachzuahmen und deren Software ohne Programmänderungen auszuführen. Aus der Sicht des Rechnerarchitekten muss ConPar Messwerte von Sensoren einlesen, multiple Tasks in Echtzeit verarbeiten und Ausgangssignale erzeugen. Typische Anwendungsgebiete von ConPar sind charakterisiert durch harte und weiche Echtzeitanforderungen bei gleichzeitig hoher Rechenleistung, die - trotz beschränkten Finanzbudgets - in weiten Grenzen von 2-256 Prozessoren skalierbar sein soll. Das ConPar-Verbindungsnetzwerk zur Interprozessor-Kommunikation basiert auf CarRing II. Die Anwendungen von ConPar liegen in der Re-Zentralisierung von ECUs, deren Zahl mittlerweile 100 erreicht hat, was im Auto  viel Platz- und Energie verbraucht und wegen der damit verbundenen Komplexität hohe Kosten und Probleme bei der Systemintegration verursacht. Ein ConPar-Rechner kann im Maximalausbau bis zu 256 ECUs ersetzen.



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